Translations:Narval/20/en: Difference between revisions

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Unfortunately, Narval's AMD processors are ''incompatible'' with the [https://en.wikipedia.org/wiki/AVX-512 AVX512] instruction set (from https://en.wikipedia.org/wiki/Skylake Skylake] onwards] on the [[Béluga/en#Node_characteristics|Béluga]] and [[Niagara#Node_characteristics|Niagara]] nodes, as well as the more recent nodes on [[Cedar#Node_characteristics|Cedar]] and [[Graham#Node_characteristics|Graham]]. Consequently, applications compiled on those relatively recent Intel nodes will probably not function on Narval and recompiling will certainly be necessary (see ''Intel compilers'' below).
Unfortunately, Narval's AMD processors are ''incompatible'' with the [https://en.wikipedia.org/wiki/AVX-512 AVX512] instruction set (from https://en.wikipedia.org/wiki/Skylake Skylake onwards) on the [[Béluga/en#Node_characteristics|Béluga]] and [[Niagara#Node_characteristics|Niagara]] nodes, as well as the more recent nodes on [[Cedar#Node_characteristics|Cedar]] and [[Graham#Node_characteristics|Graham]]. Consequently, applications compiled on those relatively recent Intel nodes will probably not function on Narval and recompiling will certainly be necessary (see ''Intel compilers'' below).

Revision as of 19:45, 18 October 2021

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Message definition (Narval)
AVX2 est pris en charge là où les nœuds ont des CPU de type Broadwell alors que les deux ensembles d’instructions (AVX2 et AVX512) le sont là où les CPU sont de type [https://fr.wikipedia.org/wiki/Skylake Skylake] ou [https://en.wikipedia.org/wiki/Cascade_Lake_(microarchitecture Cascade Lake]. Par conséquent, une application compilée dans un nœud avec un CPU Broadwell de Cedar ou Graham, incluant leurs nœuds de connexion, pourra être exécutée sur Narval, mais ne pourra pas être exécutée si elle est compilée sur Béluga ou Niagara, ou dans un nœud Skylake ou Cascade Lake de Cedar ou Graham. Dans ce dernier cas, l’application devra être recompilée (voir ''Compilateurs Intel'' ci-dessous).

Unfortunately, Narval's AMD processors are incompatible with the AVX512 instruction set (from https://en.wikipedia.org/wiki/Skylake Skylake onwards) on the Béluga and Niagara nodes, as well as the more recent nodes on Cedar and Graham. Consequently, applications compiled on those relatively recent Intel nodes will probably not function on Narval and recompiling will certainly be necessary (see Intel compilers below).

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