Translations:Narval/20/en: Difference between revisions
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Unfortunately, Narval's AMD processors are ''incompatible'' with the [https://en.wikipedia.org/wiki/AVX-512 AVX512] instruction set (from https://en.wikipedia.org/wiki/Skylake Skylake] onwards) on the [[Béluga/en#Node_characteristics|Béluga]] and [[Niagarar#Node_characteristics|Niagara]] nodes, as well as the more recent nodes on [[Cedar#Node_characteristics|Cedar]] and [[Graham | Unfortunately, Narval's AMD processors are ''incompatible'' with the [https://en.wikipedia.org/wiki/AVX-512 AVX512] instruction set (from https://en.wikipedia.org/wiki/Skylake Skylake] onwards) on the [[Béluga/en#Node_characteristics|Béluga]] and [[Niagarar#Node_characteristics|Niagara]] nodes, as well as the more recent nodes on [[Cedar#Node_characteristics|Cedar]] and [[Graham#Node_characteristics|Graham]]. Consequently, the applications compiled on those relatively recent Intel nodes will probably not function on Narval and recompiling will certainly be necessary (see ''Intel compilers'' below). |
Revision as of 18:28, 18 October 2021
Unfortunately, Narval's AMD processors are incompatible with the AVX512 instruction set (from https://en.wikipedia.org/wiki/Skylake Skylake] onwards) on the Béluga and Niagara nodes, as well as the more recent nodes on Cedar and Graham. Consequently, the applications compiled on those relatively recent Intel nodes will probably not function on Narval and recompiling will certainly be necessary (see Intel compilers below).