Translations:Narval/16/en: Difference between revisions
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=AMD processors= | =AMD processors= | ||
== Supported instructions sets == | == Supported instructions sets == | ||
Narval is equipped with 2nd and 3rd generation AMD EPYC processors which support | Narval is equipped with 2nd and 3rd generation AMD EPYC processors which support the [https://en.wikipedia.org/wiki/Advanced_Vector_Extensions#Advanced_Vector_Extensions_2 AVX2 instruction set]. This instruction set is also supported by all CPUs at [[Béluga/en#Node_characteristics|Béluga]], [[Cedar#Node_characteristics|Cedar]], [[Graham#Node_characteristics|Graham]] and [[Niagara#Node_characteristics|Niagara]]. | ||
However, all nodes at Béluga and Niagara and ''some'' nodes at Cedar and Graham also support [https://en.wikipedia.org/wiki/AVX-512 AVX512] instructions, which are ''not'' supported at Narval. |
Revision as of 21:00, 24 October 2021
AMD processors
Supported instructions sets
Narval is equipped with 2nd and 3rd generation AMD EPYC processors which support the AVX2 instruction set. This instruction set is also supported by all CPUs at Béluga, Cedar, Graham and Niagara.
However, all nodes at Béluga and Niagara and some nodes at Cedar and Graham also support AVX512 instructions, which are not supported at Narval.