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Translations:Narval/16/en: Difference between revisions
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=AMD processors= | =AMD processors= | ||
== Supported instructions sets == | == Supported instructions sets == | ||
Narval is equipped with 2nd and 3rd generation AMD EPYC processors which support [https://en.wikipedia.org/wiki/Advanced_Vector_Extensions#Advanced_Vector_Extensions_2 AVX2 instructions]. This instruction set is identical to the one used by INTEL processors on the [[Béluga/en# | Narval is equipped with 2nd and 3rd generation AMD EPYC processors which support [https://en.wikipedia.org/wiki/Advanced_Vector_Extensions#Advanced_Vector_Extensions_2 AVX2 instructions]. This instruction set is identical to the one used by INTEL processors on the [[Béluga/en#Node_characteristics|Béluga]], [[Cedar#Node_characteristics|Cedar]], [[Graham#Node_characteristics|Graham]] and [[Niagara#Node_characteristics|Niagara]] nodes. The Narval AMD processors and the Intel processors of the [https://en.wikipedia.org/wiki/Haswell_(microarchitecture) Haswell] generation are both restricted to AVX2 and earlier instructions. As such, applications compiled on a [[Cedar#Node_characteristics|Cedar]] or [[Graham#Node_characteristics|Graham]] Broadwell node should function on Narval, otherwise you will need to recompile with the appropriate architecture parameters (see ''Intel compilers'' below). | ||