Translations:Narval/16/en: Difference between revisions

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-=AMD processors=
+==AMD processors==
-== Supported instructions sets ==
+=== Supported instructions sets ===
-Narval is equipped with 2nd and 3rd generation  AMD EPYC processors which support the [https://en.wikipedia.org/wiki/Advanced_Vector_Extensions#Advanced_Vector_Extensions_2 AVX2 instruction set]. This instruction set is also supported by all CPUs at [[Béluga/en#Node_characteristics|Béluga]], [[Cedar#Node_characteristics|Cedar]], [[Graham#Node_characteristics|Graham]] and [[Niagara#Node_characteristics|Niagara]].
+Narval is equipped with 2nd and 3rd generation AMD EPYC processors which support the [https://en.wikipedia.org/wiki/Advanced_Vector_Extensions#Advanced_Vector_Extensions_2 AVX2 instruction set]. This instruction set is the same as that found on the Intel processors on the nodes at [[Béluga/en#Node_characteristics|Béluga]], [[Cedar#Node_characteristics|Cedar]], [[Graham#Node_characteristics|Graham]] and [[Niagara#Node_characteristics|Niagara]].
-However, all nodes at Béluga and Niagara and ''some'' nodes at Cedar and Graham also support [https://en.wikipedia.org/wiki/AVX-512 AVX512] instructions, which are ''not'' supported at Narval.